1. Technical Field
The present invention relates to a method and structure for forming a metallic capping interface between a damascene conductive wire/stud and a damascene conductive wiring level.
2. Related Art
FIG. 1 depicts a front cross-sectional view of an electronic structure 10 having an insulative layer 14 on a substrate layer 12, wherein the insulative layer 14 covers electronic devices that exist within and on the substrate layer 12, in accordance with the related art.
The electronic devices shown in FIG. 1 that exist within and on the substrate layer 12 include a FET 20, a FET 30, and a FET 40. The FET 20 includes a source 21, a drain 22, a gate 23, a gate insulator 24, and insulative spacers 25, wherein the source 21 and the drain 22 my be interchanged in position. The FET 30 includes a source 31, a drain 32, a gate 33, a gate insulator 34, and insulative spacers 35, wherein the source 31 and the drain 32 may be interchanged in position. The FET 40 includes a source 41, a drain 42, a gate 43, a gate insulator 44, and insulative spacers 45, wherein the source 41 and the drain 42 may be interchanged in position. As in addition to, or instead of, including the FET 20, the FET 30, and the FET 40, the substrate layer 12 may include other electronic devices such as, inter alia, bipolar transistors, diodes, etc. The electronic devices (e.g., the FET 20, the FET 30, and the FET 40), are insulatively separated from one another by insulative barriers, such as, inter alia, the shallow trench isolations 26, 36, 46, and 47.
The insulative layer 14 may include, inter alia, a insulative material 49 such as phososilicate glass (PSG) or borophososilicate glass (BPSG) formed by any method known to one of ordinary skill in the art such as by high density plasma chemical vapor deposition (HDPCVD), plasma enhanced CVD, ozone/TEOS CVD, LPCVD, etc. The thickness of the insulative layer 14 is between about 0.2 microns and about 1.5 microns and a representative thickness in the aforementioned thickness range is about 0.5 microns. A passivating layer 48 (e.g., a silicon nitride or a silicon carbide layer) may be formed on the substrate layer 12 prior to forming the insulative layer 14. The passivating layer 48 may act as an etch stop layer during a subsequent reactive ion etching (RIE) of trenches or vias 51, 52, 53, and 54 as described infra in conjunction with FIG. 2. The passivating layer 48 may also act as a mobile ion barrier, and/or as a copper diffusion barrier, or a diffusion barrier of any other metal, for protecting the substrate layer 12 and the electronic devices (i.e., the FET""s 20, 30, and 40) from subsequent etching of trenches or vias into the insulative material 49 as described infra in conjunction with FIG. 2, or from moble ions or metals (e.g., Na, Cu, etc.) diffusing into the electronic devices (i.e., the FET""s 20, 30, and 40).
FIG. 2 depicts FIG. 1 after trenches or vias 51, 52, 53, and 54 have been etched in the insulative layer 14, exposing a portion of each electronic device (i.e., the FET""s 20, 30, and 40). The process for forming the trenches or vias 51, 52, 53, and 54 may be any process known to one of ordinary skill in the art such as, inter alia, reactive ion etch (RIE) using perfluoro carbon-based or related (i.e., CHXFY, SXFX, etc.) selective etching or non-selective etching. The process for forming the trenches or vias 51, 52, 53, and 54 removes portions of both the insulative layer 14 and the passivating layer 48. The trenches or vias 51, 52, 53, and 54 may be of the same width or of different widths. The trenches or vias 51, 52, 53, and 54 serve as a template for forming conductive wires/studs (i.e., wires are formed in trenches and vias provide a conductive path that connect different wiring levels of a multilevel wiring structure) as will be described infra in conjunction with FIG. 3A. Unless otherwise stated, xe2x80x9cconductivexe2x80x9d herein means xe2x80x9celectrically conductive.xe2x80x9d
FIG. 3A depicts FIG. 2 after the trenches or vias 51, 52, 53, and 54 have been filled with conductive material to form conductive wires/studs 61, 62, 63, and 64, respectively, that conductively contact the electronic devices (i.e., the FET""s 20, 30, and 40). The conductive wires or studs 61, 62, 63, and 64 may includes any one or more conductive materials such as a semiconductor material (e.g., polysilicon), a metal (e.g., tungsten, tantalum, aluminum, TiN, copper, etc.), or a metallic alloy. Although any of preceding conductive materials may be used, an optimal conductive material is tungsten, which is typically is deposited over thin refractory conductive liners 65, 66, 67, and 68, as will be discussed infra. The conductive material may be formed by a method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., that grows the conductive material from the bottom and sidewalls of the trenches or vias 51, 52, 53, and 54. The conductive wires/studs 61, 62, 63, and 64 which include the conductive material are damascene wires/studs and collectively constitute a damascene wiring level. The conductive material so grown merges together from the bottom and sidewalls of the trenches or vias 51, 52, 53, and 54 to typically form internal seams or voids 71, 72, 73, and 74, respectively. The seams or voids 71, 72, 73, and 74 are oriented lengthwise (i.e., approximately in a direction 99) within the conductive wires/studs 61, 62, 63, and 64, respectively. The seams or voids 71, 72, 73, and 74 may extend from above bottom surfaces of the conductive wires/studs 61, 62, 63, and 64 (e.g., from above a bottom surface 55 of the conductive wire/stud 62) to top surfaces of the conductive wires/studs 61, 62, 63, and 64, respectively (e.g., to a top surface 56 of the conductive wire/stud 62). The seams or voids 71, 72, 73, and 74 are problematic as will be discussed infra in conjunction with FIG. 3B and FIG. 3D. The seams or voids 71, 72, 73, and 74 in the wire/studs 61, 62, 63, and 64, respectively, can be magnified or exacerbated by the chemical mechanical polish, etchback, and/or post planarization cleans used for damascening the metal in the trenches. The post planarization cleans can include either wet chemical etching or reactive ion etching.
Additionally, conductive liners 65, 66, 67, and 68 may be formed on the bottom and sidewalls of the trenches or vias 51, 52, 53, and 54, respectively, as shown. The conductive liners 65, 66, 67, and 68 include one or more conductive materials such as refractory metals and nitrides thereof (e.g., such as titanium, titanium nitride, etc). The conductive wire/stud 61 is conductively coupled to the gate 23 of the FET 20. The conductive wire/stud 62 is conductively coupled to the drain 22 of the FET 20. The conductive wire/stud 63 is conductively coupled to the gate 33 of the FET 30. The conductive wire/stud 64 is conductively coupled to the gate 43 and drain 42 of the FET 40. The conductive wires/studs 61, 62, 63, and 64 could alternatively be conductively coupled to source rather than drain of the FET""s 20, 30, and 40 if the positions of the sources 21, 31, and 41 were respectively interchanged with the drains 22, 32, and 42 of the FET""s 20, 30, and 40, respectively.
The filling of the trenches or vias 51, 52, 53, and 54 with the conductive material may be followed with polishing, such as by chemical mechanical polishing (CMP), or any other suitable method (e.g., etchback using a SF6 based plasma), that planarizes the top surface 17 of the insulative layer 14 and the conductive wires/studs or interconnects 61, 62, 63, and 64, and removes excess metal from the top surface 17.
FIG. 3B depicts FIG. 3A after a damascene copper wiring layer 8 has been formed on the insulative layer 14 and the conductive wires/studs 61, 62, 63, and 64. The damascene copper wiring layer 8 includes copper wiring lines 3, 4, 5, and 6, which are in conductive contact with the conductive wires/studs 61, 62, 63, and 64, respectively. The damascene copper wiring layer 8 also includes insulation 7 which insulatively separates the copper wiring lines 3, 4, 5, and 6 from one another. In order to form the copper wiring lines 3, 4, 5, and 6, trenches or vias which will include the copper of the copper wiring lines 3, 4, 5, and 6 must first be formed in the insulation. Said trenches in the insulation 7 may be formed by any method that was described supra for forming the trenches 51, 52, 53, and 54 in the insulative layer 14 of FIG. 2. After said trenches have been formed in the insulation 7, the copper of the wiring lines 3, 4, 5, and 6 may be formed as follows.
The copper wiring lines 3, 4, 5, and 6 are typically deposited respectively using one or more CVD or PVD refractory metal liners 103, 104, 105, and 106 (xcx9c5 to 25% of the line volume) such as TiN/Ta (i.e., a titanium nitride film and a tantalum film, deposited sequentially), followed by a copper deposition using damascene copper electroplating. The copper that will form the copper wiring lines 3, 4, 5, and 6 is commonly deposited using a two-step sequence comprising: (1) depositing a thin copper seed layer using, inter alia, evaporation, PVD, ionized physical vapor deposition (IPVD), CVD, or electroless plating; and (2) depositing electroplated copper on the thin seed layer. Because the vias or troughs where the copper is plated can have high aspect ratios (i.e., the aspect ratio is defined as the height of the opening to the width of the opening), one or more of the refractory metal liners 103, 104, 105, and 106, and one or more of the aforementioned copper seed layers can have poor step coverage at the via or trough bottom (i.e., the via or trough bottom thickness is less than the via or trough nominal thickness). This poor step coverage at the via or trough bottom means that the seam or void in the trenches or vias 51-54 can be exposed to the copper plating solution, which is exemplified in FIG. 3B for the copper lining 5 and the associated refractory metal liner 105. If copper plating solution accesses the seam or void in the metallized trench or via (e.g., the seam or void 73 within the conductive wires/studs 63 in the trench or via 53), then copper from the copper plating solution can become trapped inside the seam or void (e.g., the seam or void 73 within the conductive wires/studs 63 in the trench or via 53). Unfortunately, the plating solution trapped in some or all the seams or voids 71, 72, 73, and 74, within the conductive wires/studs 61, 62, 63, and 64, respectively, may expand or vaporize so as to deform, damage, or even blow up said some or all of the conductive wires/studs 61, 62, 63, and 64, during subsequent high temperature thermal processing (i.e., at a temperature above about 100xc2x0 C.). FIG. 3C depicts a top view of the conductive wiring line 3 of FIG. 3B over the associated conductive wire/stud 61 having the seam or void 71.
As an alternative illustration of the related art problems associated with the seams or voids of FIG. 3B (e.g., the seam or void 73 within the conductive wire/stud 63 in the trench or via 53 in FIG. 3B as discussed supra), FIG. 3D depicts FIG. 3B with a damascene contact or via level 200 disposed between the damascene copper wiring layer 8 of FIG. 3B and the conductive wires/studs 61, 62, 63, and 64 of FIG. 3B. The damascene contact or via level 200 in FIG. 3D includes insulation 240 and damascene wires/studs 210, 220, and 230, which respectively conductively couple the copper wiring lines 3, 5, and 6 to the conductive wires/studs 61, 63, and 64. The damascene wire/stud 220 includes a via 222, and the damascene wire/stud 230 includes a via 232. The via 222 provides a conduit from the copper wiring lines 5 to the seam or void 73 within the conductive wire/stud 63 in the trench or via 53. The conduit of the via 222 exposes the seam or void 73 within the conductive wire/stud 63 in the trench or via 53 to the copper plating solution associated with the copper wiring line 5 of the copper wiring layer. Thus, the damascene contact or via level 200 of FIG. 3D has a potential for enabling plating solution to be trapped in some or all the seams or voids 71, 72, 73, and 74, within the conductive wires/studs 61, 62, 63, and 64, respectively.
FIG. 3E illustrates FIG. 3B with an additional conductive wire/stud 60 having a conductive liner 69 and a seam or void 70, wherein the additional conductive wire/stud 60 is on the shallow trench isolation 46, and wherein an additional copper wiring line 2 of the damascene copper wiring layer 8 of FIG. 3B is on the additional conductive wire/stud 60. The additional conductive wire/stud 60 has similar physical and chemical properties, and may be similarly formed, as described supra in conjunction with FIGS. 2 and 3A for the conductive wires/studs 61, 62, 63, and 64. The additional copper wiring line 2 has similar physical and chemical properties, and may be similarly formed, as described supra in conjunction with FIG. 3B for the copper wiring lines 3, 4, 5, and 6.
A structure and method is needed for preventing copper plating solution from the damascene copper wiring layer 8 from deforming, damaging, or blowing up any or all of the conductive wires/studs 60, 61, 62, 63, and 64 (see FIG. 3B, 3D, and 3E) which are located below the damascene copper wiring layer 8 (i.e., displaced from the damascene copper wiring layer 8 in a direction 9).
The present invention provides an electronic structure, comprising:
a substrate layer that includes a first electronic device;
a first insulative layer on the substrate layer;
a first damascene conductive wire/stud having a lower portion in the first insulative layer and an upper portion above the first insulative layer;
a subtractive etch metallic cap on the upper portion of the first damascene conductive wire/stud and in conductive contact with the first damascene conductive wire/stud;
a second insulative layer on the first insulative layer, wherein the second insulative layer covers the subtractive etch metallic cap; and
a damascene conductive wiring line structure within the second insulative layer such that the damascene conductive wiring line structure is above the subtractive etch metallic cap and is conductively coupled to the subtractive etch metallic cap.
The present invention provides a method for forming an electronic structure, comprising the steps of:
providing a substrate layer that includes a first electronic device;
forming a first insulative layer on the substrate layer;
forming a first damascene conductive wire/stud in the first insulative layer;
removing a top portion of the first insulative layer such that an upper portion of the first damascene conductive wire/stud is above the first insulative layer after said removing;
forming a metallic capping layer on the first insulative layer such that the metallic capping layer is in conductive contact with the first damascene conductive wire/stud;
subtractively etching a portion of the metallic capping layer to form a subtractive etch metallic cap on the upper portion of the first damascene conductive wire/stud such that the subtractive etch metallic cap is in conductive contact with the first damascene conductive wire/stud;
forming a second insulative layer on the first insulative layer, wherein the second insulative layer covers the subtractive etch metallic cap; and
forming a damascene conductive wiring line structure within the second insulative layer such that the damascene conductive wiring line structure is above the subtractive etch metallic cap and conductively coupled to the subtractive etch metallic cap.
The present invention provides a structure and method for preventing copper plating solution from a damascene copper wiring layer from deforming, damaging, or blowing up conductive wires/studs located below the copper wiring layer.